I will be reviewing our efforts in identifying value properties of Deep Learning models that hardware accelerators can use to improve execution time performance, memory traffic and storage, and energy efficiency. Our goal it to not sacrifice accuracy and to not require any changes to the model. I will be presenting our accelerator family which includes designs that exploit these properties. Our accelerators exploit ineffectual activations and weights, their variable precision requirements, or even their value content at the bit level. Further, our accelerators also enable on-the-fly trading off accuracy for further performance and energy efficiency improvements.Finally, I will overview NSERC COHESA, a Canadian research network which targets the co-design of next generation machine learning hardware and algorithms.